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the mid-range PIC microcontroller differs from the approach taken for other processors, as a clear understanding of the application is required to ensure that when execution is returned to the previously running code the hardware is in exactly the same state it was left in. In traditional processors, the basic interrupt acknowledge operation and return from interrupt instructions save the context registers correctly, avoiding the need for the programmer to explicitly save them. The interrupt acknowledge and return from interrupt are very basic operations in the mid-range PIC microcontroller, which ts in with the RISC philosophy used to architect the device. Unfortunately, the process is complicated

TABLE 7.3 CONTEXT REGISTERS AND THE BITS THAT COULD BE AFFECTED DURING AN INTERRUPT SERVICE ROUTINE REGISTER AFFECTED BITS

All IRP, RP1, RP0, Z, DC and C All Optional only if the interrupt service routine sets and uses FSR

$1; 1 m1o FIG 9.5. h V a r i a t i o n f t e h e a t transfer coefficient with flow somewhat eases the nonlinearity of the process.

by the use of bank registers and execution pages as well as instructions that inconveniently change the context registers of the chip. There are some conventions that should be used to ensure that your interrupt handlers return execution with all context registers in the exactly same state as they were when the interrupt was acknowledged. The context registers in the mid-range PIC microcontroller are listed in Table 7.3 with bits that you should be concerned about. The list shouldn t be surprising, considering the discussion of bank addressing and interpage jumps that have been presented in this chapter. When starting an interrupt service routine, these four registers should be saved. Complicating the process is assuming that the register bank bits specify a bank other than the bank used to store the context register contents and if the PCLATH bits are not set to page 0 (where the interrupt service routine is located). The recommended entry code for the mid-range PIC microcontroller interrupt service routine (at address 4, as noted in the previous chapter) is:

org 4 Int: movwf _wreg ; Save the contents of WREG movf STATUS, w ; Save the contents of STATUS movwf _status movf PCLATH, w ; Save the contents of PCLATH movwf _pclath movf FSR, w ; Optional save the contents of FSR movwf _fsr movlw 0x1F ; Reset IRP, RP1 & RP0 (Assuming that the andwf STATUS, f ; registers accessed are in Bank 0) clrf PCLATH ; Reset PCLATH to execute out of rst page ; Test and Reset the f bit requesting the interrupt

Saving the contents of the FSR register is marked as optional because its contents only have to be saved if the interrupt service routine modi es the FSR in any way. The Test and Reset . . . code will be discussed elsewhere in the book, but I recommend that the interrupt source (if there are multiple possible sources) is checked and

the f bit is reset as soon as possible in case another interrupt request comes in while the interrupt handler is executing and becomes ignored. Before implementing this code, there are two rules you should be aware of. The rst is not to execute any goto or call instructions until after all the instructions have been executed if PCLATH has not been reset, you could have a jump to an unexpected address. For example, the code:

org 4 Int: goto ;

(continued)

IntHandler: movwf _w movf STATUS, w movwf _status movf PCLATH, w :

; ; ;